Energy-Efficient High-Speed SAR ADCs in CMOS

An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sampling frequency is presented. The ADC fulfills all specifications for 100 Gb/s ITU-OTU4 communication over long-distance optical fiber channels. It is based on a SAR ADC, known for its superior energy efficiency and suitability for deep-submicron digital CMOS processes, as the comparator is the only true analog element. Several improvements to existing SAR ADC architectures are presented. Alternate comparators are used to increase the sampling speed at no power and area penalty, and dynamic memory is used to reduce latency in the CDAC feedback. A deep-trench capacitor-based reference buffer significantly reduces power at low output impedance, and a differential CDAC with constant common mode and fractional reference voltages optimizes comparator performance and silicon area. The 64× interleaved ADC consists of a dedicated sampling and interleaving block and 64 SAR ADCs. Four interleaved passive samplers based on a sampling switch with in-line 1:4 demultiplexer provide an initial 1:16 interleaving with high linearity and more than 20 GHz input bandwidth while using only a single supply voltage.

Harpe, Pieter
Baschirotto, Andrea
Makinwa, Kofi
Published in:
High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 45-63
Switzerland, Springer Inernational Publishing

 Record created 2014-10-08, last modified 2018-03-17

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