Novel Configurable Logic Block Architecture Exploiting Controllable-Polarity Transistors, invited paper
Controllable-polarity transistors exhibit a device-level configurability. Indeed, they can be dynamically configured between n- type and p-type. Such property can be exploited in <i>Field Programmable Gate Arrays</i> (FPGAs) to replace traditional <i>Look-Up Tables</i> (LUTs) by more powerful configurable units. We report here on a new FPGA logic block architecture, called <i>MCluster</I>, that takes a direct advantage of configurable transistors. The performance of the approach is evaluated and compared to its traditional <i>Complementary Metal-Oxide- Semiconductor</i> (CMOS) counterpart at 22-nm technology node. We note an average saving of 64% in area×delay×power product.
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