Loading...
conference paper
Pattern-Based FPGA Logic Block and Clustering Algorithm
2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL)
In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks.
Loading...
Name
fpl14_final.pdf
Access type
openaccess
Size
357.31 KB
Format
Adobe PDF
Checksum (MD5)
71f3b9b6c26da95c67ecb31ca51c1185