Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-<i>V</i><sub>T</sub>) or even to the subthreshold (sub-<i>V</i><sub>T</sub>) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near-<i>V</i><sub>T</sub> and sub-<i>V</i><sub>T</sub> operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub- voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near- voltage for robust read. Energy characterization is performed at nominal, near-<i>V</i><sub>T</sub> , and sub-<i>V</i><sub>T</sub> supply voltages. The minimum energy point is reached for near-<i>V</i><sub>T</sub> read operation with a total read+write energy of 735 fJ.

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IEEE Transactions on Circuits and Systems Part 1 Regular Papers, 61, 11, 3155-3164
Piscataway, Institute of Electrical and Electronics Engineers

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 Record created 2014-09-30, last modified 2020-07-29

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