Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.


Published in:
2013 Ieee Workshop On Signal Processing Systems (Sips), 177-182
Presented at:
IEEE Workshop on Signal Processing Systems (SiPS)
Year:
2013
Publisher:
New York, Ieee
ISSN:
2162-3562
ISBN:
978-1-4673-6238-2
Keywords:
Laboratories:




 Record created 2014-06-02, last modified 2018-09-13


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