Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and router-level switching activity. We specifically focus on memory subsystem traffic, as it comprises the bulk of NoC load in a CMP. By transmitting only the flits that contain words predicted useful using a novel spatial locality predictor, our scheme seeks to reduce network activity. We aim to further lower NoC energy through microarchitectural mechanisms that inhibit datapath switching activity for unused words in individual flits. Using simulation-based performance studies and detailed energy models based on synthesized router designs and different link wire types, we show that 1) the prediction mechanism achieves very high accuracy, with an average rate of false-unused prediction of just 2.5 percent; 2) the combined NoC energy savings enabled by the predictor and microarchitectural support is 36 percent, on average, and up to 57 percent in the best case; and 3) there is no system performance penalty as a result of this technique.


Published in:
IEEE Transactions on Computers, 63, 3, 543-556
Year:
2014
Publisher:
Los Alamitos, Institute of Electrical and Electronics Engineers
ISSN:
0018-9340
Keywords:
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 Record created 2014-05-02, last modified 2018-03-17

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