Ultra low power design of hardware efficient CS-Based compression scheme in WBSN
Ultra-low power optimization is a challenging research topic in the de- sign of the sensor front-ends, especially in the area of Wireless Body Sensor Nodes (WBSN), where a limited amount of power and hardware resources are available. In this talk, I analyze the potential of the emerging compressed sensing (CS) paradigm for low-complexity and energy-efficient ECG sensing and data compression for storage or transmission, considering both software and hardware aspects. First, I discuss the power efficiency of digital CS, when implemented as a compression technique on a WBSN, illustrating novel optimization techniques to enhance the performance of reconstruction algorithms. These new techniques fully leverage the prior information (beyond simple sparsity) from the underlying signal, improving the compression results for both single lead and joint multi-lead ECG compression. Then, I present novel hardware optimization approaches targeting the design of ultra-low power CS-based analog front-ends in order to make them suitable for WBSN applications. Furthermore, I propose a new hybrid front- end design based on CS that can effectively reduce the power consumption by merging the sensing and compression phases as a single step. Finally, I overview the effects of technology scaling in the design of low- cost processing integrated circuits for CS compression in WBSNs; and ad- vocate the use of a novel robust CS technique to successfully recover the compressed data in presence of unbounded error levels in ultra-low power memories due to aggressive voltage scaling. Moreover, this proposed tech- nique achieves significant energy savings on WBSNs with respect to state-of- the-art designs in nano-scale technologies.
Record created on 2014-04-26, modified on 2016-08-09