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conference paper

Rapid Design Space visualisation through hardware/software partitioning

Spacey, Simon A.
•
Luk, Wayne
•
Kelly, Paul H. J.
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2009
2009 5th Southern Conference on Programmable Logic (SPL)
2009 5th Southern Conference on Programmable Logic (SPL)

This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before investing in a particular hardware/ software codesign. 3SP uses a novel program execution model to integrate comprehensive hardware characteristics including clock speed, number of execution units, issue rates, bandwidths and latencies with software program execution, parallelism, control and data flow measurements to estimate codesign performance for evaluating opportunities for hardware acceleration.

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Type
conference paper
DOI
10.1109/SPL.2009.4914913
Author(s)
Spacey, Simon A.
Luk, Wayne
Kelly, Paul H. J.
Kuhn, Daniel  
Date Issued

2009

Publisher

IEEE

Published in
2009 5th Southern Conference on Programmable Logic (SPL)
ISBN of the book

978-1-4244-3847-1

Start page

159

End page

164

Subjects

Acceleration

•

Accelerometers

•

Bandwidth

•

Clocks

•

Computer architecture

•

Delay

•

Hardware

•

Software performance

•

Space exploration

•

Visualization

URL

URL

http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&tp=&arnumber=4914913
Editorial or Peer reviewed

NON-REVIEWED

Written at

OTHER

EPFL units
RAO  
Event nameEvent placeEvent date
2009 5th Southern Conference on Programmable Logic (SPL)

São Carlos, Brazil

1-3 04 2009

Available on Infoscience
January 29, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/100243
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