Rapid Design Space visualisation through hardware/software partitioning

This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before investing in a particular hardware/ software codesign. 3SP uses a novel program execution model to integrate comprehensive hardware characteristics including clock speed, number of execution units, issue rates, bandwidths and latencies with software program execution, parallelism, control and data flow measurements to estimate codesign performance for evaluating opportunities for hardware acceleration.


Published in:
2009 5th Southern Conference on Programmable Logic (SPL), 159-164
Presented at:
2009 5th Southern Conference on Programmable Logic (SPL), São Carlos, Brazil, 1-3 04 2009
Year:
2009
Publisher:
IEEE
ISBN:
978-1-4244-3847-1
Keywords:
Laboratories:




 Record created 2014-01-29, last modified 2018-09-13

External link:
Download fulltext
URL
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)