Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first step, addressing bias-dependency of various key MOSFET parameters (e. g. series resistance, channel width and gate-channel capacitance), non-uniform electron density due to corners and quantization. A significant bias-dependent series resistance variation in JL MOSFETs is reported above flat-band, leading to a significant mobility extraction accuracy drop of similar to 50%. All quasistationary device simulations were done on 100 nm long channel devices with 5-20 nm NW width, 2 nm SiO2 gate oxide thickness and 1x10(19) cm(-3) n-type channel doping using a constant mobility model (100 cm(2)/V.s).


Published in:
2013 14Th International Conference On Ultimate Integration On Silicon (Ulis), 106-109
Presented at:
14th International Conference on Ultimate Integration on Silicon (ULIS)
Year:
2013
Publisher:
New York, IEEE
ISSN:
2330-5738
ISBN:
978-1-4673-4802-7
Keywords:
Laboratories:




 Record created 2013-12-09, last modified 2018-03-17


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