Porting an MPEG-HEVC decoder to a low-power many-core platform
After several generations of video coding standards, MPEG High Efficient Video Coding (HEVC) is likely to emerge as the video coding standards for HD and Ultra-HD TV. HEVC decoding is expected to be less computationally demanding and to provide a higher level of potential intrinsic parallelism. A many-core platform such as the STM STHORM appears to be a very good candidate for supporting low-power HEVC implementations capable of exploiting the different intrinsic parallelization options. This work explores the potential of HEVC wavefront and tiles algorithms implementation on the STHORM. Different partitioning options of an HEVC specified at high level using the standard RVC-CAL dataflow language are presented. Performances are measured and profiled on the STHORM platform by repartitioning and refactoring the dataflow software according to performance objectives.