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conference paper
Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology
2011
CAS 2011 Proceedings (2011 International Semiconductor Conference)
This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0.6 to 3 milliSiemens, in agreement with the expected values. © 2011 IEEE.
Type
conference paper
Authors
Publication date
2011
Publisher
Published in
CAS 2011 Proceedings (2011 International Semiconductor Conference)
Start page
325
End page
328
Peer reviewed
REVIEWED
Event name | Event place | Event date |
Sinaia, Romania | 17-19 October 2011 | |
Available on Infoscience
August 7, 2013
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