An Ultra-High Speed Emulator Dedicated to Power System Dynamics Computation Based on a Mixed-Signal Hardware Platform

This paper presents an ultra-high speed hardware platform dedicated to power system dynamic (small signal) and transient (large signal) stability. It is based on an intrinsic parallel architecture which contains hybrid mixed-signal (analog and digital) circuits. For a given model, this architecture overcomes the speed of the numerical simulators by means of the so-called emulation approach. Indeed, the emulation speed does not depend on the power system size. This approach is nevertheless not competing against high-performance numerical simulators in term of accuracy and model complexity. It targets to complement the numerical simulators with the advantage of speed, portability, low cost and autonomous functioning. The proof of concept is a flexible and modular 96-node hardware platform. It is based on a reconfigurable array of power system buses called Field Programmable Power Network System (FPPNS). Details on this hardware are given. Two benchmark topologies with, respectively, 17 nodes and 57 nodes are provided. Comparisons with a digital simulator are done in terms of speed and accuracy. The calibration of the system is explained and different applications are proposed and discussed. The promising results of this hardware platform show that the design of a fully integrated solution containing hundreds of power system buses can be achieved in order to provide a low cost solution.

Publié dans:
Ieee Transactions On Power Systems, 28, 4, 4228-4236
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc

 Notice créée le 2013-06-28, modifiée le 2019-12-05

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