Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications

Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art.


Published in:
Proc. of the 38th International Conference on Acoustics, Speech, and Signal Processing
Presented at:
38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vancouver, Canada, May 26-31, 2013
Year:
2013
Publisher:
IEEE
Keywords:
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 Record created 2013-06-03, last modified 2018-09-13

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