Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications.


Published in:
Proceedings of the 50th Design Automation Conference (DAC 2013)
Presented at:
50th Design Automation Conference (DAC 2013), Austin, Texas, USA, June 2-6, 2013
Year:
2013
Keywords:
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 Record created 2013-05-23, last modified 2018-09-13

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