STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove some instruction stalls in exchange for error-prone instrumentation to the code base, or for a sharp increase the L1-I cache unit area and power. Others reduce instruction miss latency by better utilizing a shared L2 cache. SLICC, a recently proposed thread migration technique that exploits transaction instruction locality, is promising for high core counts but performs sub-optimally or may hurt performance when running on few cores. This paper corroborates that OLTP transactions exhibit significant intra- and inter-thread overlap in their instruction footprint, and analyzes the instruction stall reduction benefits. This paper presents STREX, a hardware, programmer-transparent technique that exploits typical transaction behavior to improve instruction reuse in first level caches. STREX time-multiplexes the execution of similar transactions dynamically on a single core so that instructions fetched by one transaction are reused by all other transactions executing in the system as much as possible. STREX dynamically slices the execution of each transaction into cache-sized segments simply by observing when blocks are brought in the cache and when they are evicted. Experiments show that, when compared to baseline execution on 2 -- 16 cores, STREX consistently improves performance while reducing the number of L1 instruction and data misses by 37\% and 14\% on average, respectively. Finally, this paper proposes a practical hybrid technique that combines STREX and SLICC, thereby guaranteeing performance benefits regardless of the number of available cores and the workload's footprint.

Published in:
Proceedings of the 40th International Symposium on Computer Architecture
Presented at:
40th International Symposium on Computer Architecture, Tel-Aviv, Israel, June 23-27, 2013

 Record created 2013-04-02, last modified 2018-01-28

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