Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

In this letter, we report the performance of high-kappa/metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (I-on/I-off) > 10(6). For the first time, an SS lower than 70 mV/dec is achieved at L-G = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.


Published in:
IEEE Electron Device Letters, 33, 9, 1225-1227
Year:
2012
Publisher:
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc
ISSN:
0741-3106
Keywords:
Laboratories:




 Record created 2013-02-27, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)