Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics simultaneously. In this paper, we show that, by engineering of the contacts and by constructing independent double-gate structures, the device polarity can be electrostatically programmed to be either n- or p-type. Such a device enables a compact realization of XOR-based logic functions at the cost of a denser interconnect. To mitigate the added area/routing overhead caused by the additional gate , an approach for designing an efficient regular layout, called Sea-of-Tiles is presented. Then, specific logic synthesis techniques, supporting the higher expressive power provided by this technology, are introduced and used to showcase the performance of the controllable-polarity NWFETs circuits in comparison with traditional CMOS circuits.


Published in:
Proceedings of the Design, Automation & Test in Europe Conference (DATE 2013)
Presented at:
Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, March 18-22, 2013
Year:
2013
ISBN:
978-3-9815370-0-0
Keywords:
Laboratories:




 Record created 2013-01-15, last modified 2018-03-18

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