This paper proposes alternative architectures to perform a circular correlation using the Fast Fourier Transform (FFT) by decomposing the initial circular correlation into several smaller circular correlations. The approach used is similar to the Fast Finite Impulse Response (FIR) Algorithms (FFAs). These architectures improve the performance in terms of reduced processing time or resource usage, and consequently lower the energy consumption. The results can be applied to any system that performs circular convolution or correlation. In this paper, the application is the acquisition of Global Navigation Satellite System (GNSS) signals with the FFT-based Parallel Code-phase Search (PCS), and more precisely on the GPS L1 C/A signal, when the target considered is a Field Programmable Gate Array (FPGA). In this context, it is for example shown that it is possible with one of the proposed architectures to reduce the logic usage by 11 %, the memory usage by 41 %, and the Digital Signal Processing (DSP) block usage by 32 %, while keeping the same processing time. With another architecture, it is shown that the processing time can be halved by increasing the logic usage by only 35 %, while reducing the memory usage and keeping the same DSP usage. Note that the proposed approach is not based on an approximation of the traditional method, but a modified implementation providing the same result. Thus, there is no loss of sensitivity.