Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/design co-optimization approach for designing logic tiles for double-gate silicon nanowire field effect transistors (DG- SiNWFET) technology. A compact Verilog-A model of the device is extracted from TCAD simulations. Cell libraries with different tile configurations are mapped to study the performance of DG-SiNWFET technology at various technology nodes. With an optimal tile size comprising of 6 vertically-stacked nanowires, we observe 1.6x improvement in area, 2x decrease in the leakage power and 1.8x improvement in delay when compared to Si- CMOS.

Published in:
Proceedings of the IEEE /ACM International Symposium on Nanoscale Architectures (NANOARCH '12)
Presented at:
IEEE /ACM International Symposium on Nanoscale Architectures (NANOARCH '12), Amsterdam, Netherlands, July 4-6, 2012

 Record created 2012-07-10, last modified 2019-03-16

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