Physical Design Issues in 3-D Integrated Technologies

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

Published in:
VLSI-SOC: Design Methodologies for SoC and SiP, 313, 1-21
Presented at:
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2008), Rhodes, Greece, Oct 13-15, 2008
Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa

 Record created 2012-06-25, last modified 2018-03-17

Rate this document:

Rate this document:
(Not yet reviewed)