Methodology For The Hardware/Software Co-Design Of Dataflow Programs

New generations of multi-core processors and reconfigurable hardware platforms are expected to provide a dramatic increase of processing capabilities. However, one obstacle for exploiting all the promises of such new platforms is the legacy of current applications and the development methodologies used, which is deeply rooted in a sequential way of thinking. A paradigm shift is necessary at all levels of application development to yield portable and efficient implementations, capable of exploiting the full potential of such platforms. Dataflow programming is an alternative approach that address the problem of providing portable and scalable parallel applications. Dataflow programming is able to explicitly expose the intrinsic parallelism of applications. This paper presents a hardware/software co-design methodology that starting from a unique dataflow program enables, by the direct synthesis of both hardware (HDL) and software components (C/C++), to map a signal processing application onto heterogeneous systems architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of the MPEG-4 Simple Profile decoder onto an heterogeneous platform are also provided to show the capabilities and flexibility of the approach.


Published in:
2011 Ieee Workshop On Signal Processing Systems (Sips), 174-179
Presented at:
IEEE Workshop on Signal Processing Systems (SiPS), Beirut, LEBANON, Oct 04-07, 2011
Year:
2011
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
978-1-4577-1921-9
Keywords:
Laboratories:




 Record created 2012-06-25, last modified 2018-03-17


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