System design of a 24 GHz phased-array front-end for low-power applications

This paper deals with the design of a 4-channel phased-array receiver Front-End (FE) architecture working at 24 GHz. Targeting low power applications such as radar sensors and medium bit-rate transceivers, a local oscillator shifting architecture is proposed and designed. Some fundamental blocks have been developed in 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, namely a low noise amplifier, a vector modulation phase shifter and a quadrature voltage controlled oscillator. Their post-layout simulated data have been used inside the Advanced Design System software environment, together with state-of-the-art models for the mixer and combiner, in order to evaluate the layout effects on the whole FE performance. The proposed phased-array receiver system provides continuous beam steering operation, a noise figure of 3.5 dB and a power consumption of less than 200mW.

Published in:
Proceedings of the 8th Conference on Ph.D. Research in Microelectronics & Electronics, 285-288
Presented at:
PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics, Aachen, Germany, June 12-15, 2012

Note: The status of this file is: EPFL only

 Record created 2012-06-21, last modified 2018-01-28

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