Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecting the appropriate number of layers. For the purpose of evaluation, dies have been fabricated using a commodity UMC 90nm CMOS process and stacked using a in-house, Via-Last copper TSV process. Each die, featuring four cores interconnected by a Network-on-Chip (NoC), has been designed for a maximum operating frequency of 400MHz resulting in 3.2Gbps data bandwidth.


Published in:
Proceedings of the 49th Design Automation Conference (DAC 2012)
Presented at:
49th Design Automation Conference (DAC 2012), San Francisco, June 2-6, 2012
Year:
2012
Publisher:
San Francisco
Laboratories:




 Record created 2012-06-14, last modified 2018-03-17


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