Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs
The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.
Keywords: Circuit noise , Coupling circuits , Electronic design automation and methodology , Inductance , Iterative methods , Noise reduction , Radio frequency , System-on-a-chip , Transceivers , Voltage-controlled oscillators
Record created on 2012-05-15, modified on 2016-08-09