Fast and Scalable Temperature-driven Floorplan Design in 3D MPSoCs

• Presented at: 13th IEEE Latin American Test Workshop (LATW2012), Quito, Ecuador, April 10-13, 2012
• Accepted in: Proceedings of the 13th IEEE Latin American Test Workshop (LATW2012), p. 98-103
• New York: IEEE Press, 2012

Temperature-driven floorplaners have been recently proposed to alleviate the thermal problem in 3D multi-processor systems-on-chip (MPSoC). However, the proposed algorithms fail to provide fast placement of the modules when the complexity and the number of functional units in the stack increases. This paper proposes a fast and scalable CPU-GPU implementation of a multi-objective evolutionary algorithm that performs a thermal optimization of complex 3D MPSoCs, capable of obtaining optimal solutions in a reduced time. A comparative study shows that this work outperforms other proposals and reduces the computational time of the thermal optimization of complex architectures.

Keywords: 3D-IC ; Therma-Aware Design ; GPU

Reference

• EPFL-CONF-175787

Record created on 2012-03-19, modified on 2017-05-10