Fast and Scalable Temperature-driven Floorplan Design in 3D MPSoCs

Temperature-driven floorplaners have been recently proposed to alleviate the thermal problem in 3D multi-processor systems-on-chip (MPSoC). However, the proposed algorithms fail to provide fast placement of the modules when the complexity and the number of functional units in the stack increases. This paper proposes a fast and scalable CPU-GPU implementation of a multi-objective evolutionary algorithm that performs a thermal optimization of complex 3D MPSoCs, capable of obtaining optimal solutions in a reduced time. A comparative study shows that this work outperforms other proposals and reduces the computational time of the thermal optimization of complex architectures.


Published in:
Proceedings of the 13th IEEE Latin American Test Workshop (LATW2012), 98-103
Presented at:
13th IEEE Latin American Test Workshop (LATW2012), Quito, Ecuador, April 10-13, 2012
Year:
2012
Publisher:
New York, IEEE Press
Keywords:
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 Record created 2012-03-19, last modified 2018-03-17

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