Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm2/V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400 K and a VTH drift of −1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.


Published in:
Solid State Electronics (selected papers from the IEEE ESSDERC 2011 conference), 74, 114-120
Year:
2012
Publisher:
Elsevier
Keywords:
Laboratories:




 Record created 2012-02-29, last modified 2018-03-17

n/a:
Download fulltextPDF
External link:
Download fulltextURL
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)