A CMOS Compatible Chip-to-Chip 3D Integration Platform

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-level. A parylene deposition technique developed throughout this research provides a very flat wafer surface after chip embedding, thus, photoresist spin-coating and patterning can easily be performed in wafer-level. For a full-wafer exposure by a mask aligner, 5 mu m mask-to-chip alignment accuracy is achieved in average. In the preliminary tests, two dummy chips are successfully bonded, and TSVs with parylene sidewall passivation and electroplated Cu metallization are fabricated. The daisy-chain resistance measurements demonstrate average TSV resistance of 0.5 Omega. The proposed technique introduces a simple and low-cost solution not only for 3D integration technology but also for applications involving CMOS post-processing in general, especially when the full-wafer CMOS is not affordable or not possible to post-process due to compatibility issues.

Published in:
Proceedings of the 62nd Electronic Components and Technology Conference (ECTC), 555-560
Presented at:
Electronic Components and Technology Conference (ECTC), San Diego, California, USA, May 29-June 2, 2012
New York, IEEE

 Record created 2012-02-28, last modified 2018-03-18

Rate this document:

Rate this document:
(Not yet reviewed)