Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fabrication methodology is demonstrated for curved and straight SiNW arrays with different shapes and levels. Ultra-high density SiNW arrays with round or rhombic cross-sections diameters as low as 10 nm are demonstrated for vertical and horizontal spacing of 60 nm. The uniqueness of the technique, which achieves several advantages such as bulk-Si processing, low-thermal budget, and wide process window makes this fabrication method suitable for a very broad range of applications such as nano-electro-mechanical systems (NEMS), nano-electronics and bio-sensing.


Published in:
Microelectronic Engineering, 88, 10, 3127-3132
Year:
2011
Publisher:
Elsevier
ISSN:
0167-9317
Keywords:
Laboratories:




 Record created 2011-12-22, last modified 2018-12-03

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