Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors).


Published in:
Fpga 11: Proceedings Of The 2011 Acm/Sigda International Symposium On Field Programmable Gate Arrays, 237-246
Presented at:
19th Annual ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb 27-Mar 01, 2011
Year:
2011
Publisher:
Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa
ISBN:
978-1-4503-0554-9
Keywords:
Laboratories:




 Record created 2011-12-16, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)