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conference paper
Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains
2011
Fpga 11: Proceedings Of The 2011 Acm/Sigda International Symposium On Field Programmable Gate Arrays
Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors).
Type
conference paper
Web of Science ID
WOS:000290931400036
Authors
Publication date
2011
Published in
Fpga 11: Proceedings Of The 2011 Acm/Sigda International Symposium On Field Programmable Gate Arrays
ISBN of the book
978-1-4503-0554-9
Start page
237
End page
246
Peer reviewed
NON-REVIEWED
EPFL units
Event name | Event place | Event date |
Monterey, CA | Feb 27-Mar 01, 2011 | |
Available on Infoscience
December 16, 2011
Use this identifier to reference this record