Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

In this paper, a modeling methodology is validated based on an enhanced model of the diode, that we have developed to simulate substrate current coupling mechanisms on a typical H -bridge structure. An equivalent schematic based on an enhanced model of the diode was previously proposed to account for minority and majority carrier propagation in the substrate and implemented in Verilog-A code. In this study, the injected parasitic substrate current from high-voltage MOSFETs structure is simulated in a circuit-level simulator and with a finite element method, as well. Both are compared to measurements and confirm a very good agreement up to 400 K. Not only the simulation resources needed by the proposed equivalent schematics are greatly reduced with regard to the finite element approach, but this circuit-level modeling methodology is fully compatible with Spice-like simulations of complex ICs. © 2011 IEEE.

Published in:
IEEE Transactions on Power Electronics, 26, 10, 2788-2793

 Record created 2011-11-07, last modified 2018-01-28

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