This paper focuses on a new pipelined processing unit architecture dedicated to mixed-signal power system emulation. Prior research in this field has proven that analog emulation overcomes the speed limits of numerical simulators with reliable accuracy. Then, a new concept based on field programmable power network system (FPPNS) has been developed in order to gain in term of flexibility. It is based on a hybrid architecture where grid equations are solved analogically and generator and load equations are solved digitally. A first platform based on a developed application specific integrated circuit has validated the concept with a 16-node topology. The present work aims to extend the size of the emulation hardware (up to 100 nodes) as well as to increase the speed. Therefore the digital equations are solved on an embedded FPGA containing four parallel pipelined processing unit which are interfaced to the analog emulator. Speed results are provided and compared with a reference numerical simulator. © 2011 IEEE.