A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
Roth, C.; Meinerzhagen, Pascal Andreas; Studer, C.; Burg, Andreas Peter
2010

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Abstract

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm2 and achieves a maximum throughput of 680 Mbps at 346MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.

Details

Title A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
Author(s) Roth, C. ; Meinerzhagen, Pascal Andreas ; Studer, C. ; Burg, Andreas Peter
Published in 2010 IEEE Asian Solid-State Circuits Conference
Pages 1-4
Conference 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, November 8-10, 2010
Date 2010
Publisher IEEE
DOI https://doi.org/10.1109/ASSCC.2010.5716618
Laboratories TCL
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > TCL - Telecommunications Circuits Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2011-08-21

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