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conference paper
Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems
2011
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11
This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.
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Name
gls121-meinerzhagen.pdf
Type
Postprint
Access type
openaccess
Size
146.93 KB
Format
Adobe PDF
Checksum (MD5)
8aea290dc0bb3838eb2a0c0f1f169cea