A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration.


Published in:
Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL 2011), 1, 1, 177-180
Presented at:
21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Greece, September 5-7, 2011
Year:
2011
Publisher:
New York, ACM and IEEE Press
ISBN:
978-0-7695-4529-5
Keywords:
Laboratories:




 Record created 2011-08-11, last modified 2018-09-13

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