Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be reliable throughout their lifetime. New microarchitectures require new reliability-aware design methods that can face these challenges without significantly increasing cost and performance. In this paper we present a complete analysis of reliability for the register file architecture of the Leon 3 processor. The analysis conducted is supported by the use of an accurate HW/SW FPGA-based emulation platform that enables a complete design space exploration of thermal and reliability metrics during the execution of an extended set of benchmarks, in a very limited amount of time. The effect of various compiler optimizations and register assignments on the reliability of the register file is then analyzed. Our results quantify the respective effects of these different factors and enable us to design a reliability-aware register file assignment policy that consistently improves the Mean-Time-To-Failure figure (20% on average) for the various types of applications.


Published in:
Proceedings of the 2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘08), 1, 1, 61-66
Presented at:
2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘08), Hawaii, USA, January 21-23, 2008
Year:
2008
Publisher:
New York, IEEE Computer Society
ISBN:
978-1-4244-6465-4
Keywords:
Laboratories:




 Record created 2011-08-10, last modified 2018-03-17

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