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conference paper
Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography
2011
Proceedings of the 37th International Conference on Micro and Nano Engineering (MNE)
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Name
MNE2011_2.pdf
Access type
openaccess
Size
306.04 KB
Format
Adobe PDF
Checksum (MD5)
a01fbd7fd64d05205d1540d9221be040