Home > 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks
 

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks

Seiculescu, Ciprian ; Murali, Srinivasan ; Benini, Luca ; De Micheli, Giovanni[...]

Editor(s):
Sheibanyrad, Abbas
Pétrot, Frédéric
Jantsch, Axel
Published in:
3D Integration for NoC-based SoC Architectures, 3, 193-223
Year:
2011
Publisher:
Springer New York
ISBN:
978-1-4419-7618-5
DOI:
10.1007/978-1-4419-7618-5_9
Laboratories:
LSI1

Record appears in:
Scientific production and competences > STI - School of Engineering > IEL - Institute of Electrical Engineering > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Work produced at EPFL
Book chapters
Published



 Record created 2011-07-22, last modified 2018-09-13


Rate this document:

Rate this document:
1
2
3
4
5
 
(Not yet reviewed)