A DRAM Centric NoC Architecture and Topology Design Approach

Most communication traffic in today’s System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM controller. In this paper, we motivate the use of a separate network for the DRAM traffic and justify the power overhead and performance improvement obtained, when compared to traditional solutions. We also show how the topology of this DRAM network can be designed and optimized to account for the funnel-shaped pattern. Our experiments on a realistic SoC multimedia benchmark shows a large reduction in power consumption and improvement in performance when compared to existing solutions.


Published in:
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 54-59
Presented at:
IEEE Computer Society Annual Symposium on VLSI, Chennai, India, July 4-6, 2011
Year:
2011
Publisher:
Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa
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 Record created 2011-07-22, last modified 2018-09-13

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