Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS.