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conference paper
Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes
2008
2008 42Nd Asilomar Conference On Signals, Systems And Computers
We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11n standard and achieves a throughput of 780 M bit/s with a core area of 3.39 mm(2) in 0.18 mu m CMOS technology.
Type
conference paper
Web of Science ID
WOS:000274551001001
Authors
Publication date
2008
Published in
2008 42Nd Asilomar Conference On Signals, Systems And Computers
ISBN of the book
978-1-4244-2940-0
Start page
1137
End page
1142
Subjects
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
Pacific Grove, CA | Oct 26-29, 2008 | |
Available on Infoscience
June 6, 2011
Use this identifier to reference this record