Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Studer, C.; Preyss, Nicholas Alexander; Roth, C.; Burg, A.

Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Studer, C. ; Preyss, Nicholas Alexander ; Roth, C. ; Burg, A.

We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11n standard and achieves a throughput of 780 M bit/s with a core area of 3.39 mm(2) in 0.18 mu m CMOS technology.

Published in:

2008 42Nd Asilomar Conference On Signals, Systems And Computers, Vols 1-4, 1137-1142

Presented at:

42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 26-29, 2008

Year:

2008

Publisher:

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

ISBN:

978-1-4244-2940-0

Keywords:

Parity-Check Codes ; Design ; System