Receiver design for multi-antenna wireless communications

Algorithm choices and corresponding VLSI architectures for spatial multiplexing receivers in multiple-input multiple-output (MIMO) communication systems are described in this paper. Implementations of linear and successive interference cancellation receivers are compared to implementations of maximum likelihood (ML) decoders that attain optimum bit error rate performance. The presented designs provide reference for the true silicon complexity of the algorithms under consideration and help to identify the limits with respect to practical implementations.


Published in:
2005 PhD Research in Microelectronics and Electronics, Vols 1 and 2, Proceedings, 231-234
Presented at:
International Conference on PhD Research in Microelectronics and Electronics (PRIME 2005), Lausanne, SWITZERLAND, 2005
Year:
2005
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
0-7803-9345-7
Laboratories:




 Record created 2011-06-06, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)