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conference paper
An ASIC implementation of adaptive arithmetic coding
2002
Thirty-Sixth Asilomar Conference On Signals, Systems & Computers - Conference Record
In this work, we present an improved version of an ASIC implementation of the adaptive arithmetic coding algorithm which uses a two-level memory hierarchy. We propose algorithmic modifications and a special hardware structure to speed-up the design without degrading the compression ratio obtained using this memory hierarchy. Moreover, several new features which increase the compression efficiency are introduced. Finally, a VLSI implementation based on the results of our work is presented.
Type
conference paper
Web of Science ID
WOS:000182548900203
Authors
Publication date
2002
Published in
Thirty-Sixth Asilomar Conference On Signals, Systems & Computers - Conference Record
ISBN of the book
0-7803-7576-9
Volume
2
Start page
1078
End page
1083
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
PACIFIC GROVE, CA | Nov 03-06, 2002 | |
Available on Infoscience
June 6, 2011
Use this identifier to reference this record