Bandwidth-Constrained Mapping of Cores onto NoC Architectures

• Presented at: Design, Automation, & Test in Europe (DATE), Paris, France, February 16-20, 2004
• Published in: Proceedings of Design, Automation, & Test in Europe (DATE)
• Publication date: 2004

We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the edge of congestion. Typical applications are in the area of multi-media processing. We consider a mesh-based Networks on Chip (NoC) architecture, and we explore the assignment of cores to mesh cross-points so that the traffic on links satisfies bandwidth constraints. A single-path deterministic routing between the cores places high bandwidth demands on the links. The bandwidth requirements can be significantly reduced by splitting the traffic between the cores across multiple paths. In this paper, we present NMAP, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay. The NMAP algorithm is presented for both single minimum-path routing and split-traffic routing. The algorithm is applied to a benchmark DSP design and the resulting NoC is built and simulated at cycle accurate level in SystemC using macros from the ?pipes library. Also, experiments with six video processing applications show significant savings in bandwidth and communication cost for NMAP algorithm when compared to existing algorithms.

Keywords: Systems on Chips, Networks on Chips, cores, mapping, bandwidth, routing

Reference

• EPFL-CONF-165550
• doi:10.1109/DATE.2004.1269002

Record created on 2011-05-05, modified on 2017-05-12