A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Nowadays, multi-core Systems-on-Chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms (e.g., FPGAs) is growing, as they increase the ability of the initial design to adapt to future modifications. This work presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not know at design-time, preserving the mapping of the original system. We apply our design flow to a real–world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.

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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 30, 8, 1211-1224
Institute of Electrical and Electronics Engineers

 Record created 2011-03-31, last modified 2018-03-17

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