Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistor

In this work a high-k double-gate pentacene field-effect transistor architecture is presented. The devices are fabricated on a flexible polyimide substrate by three aligned levels of stencil lithography combined with standard photolithography. ALD-deposited high-k HfO2 and parylene D device passivation, together with Pt top-gate deposition provide very good electrostatic control of the channel, showing low leakage current and improved subthreshold. The ION/IOFF ratio is of the order of 106 and the IOFF lower than 0.1 pA/μm. We also report a comparison of the normal, FET-like (VD < 0) and reverse, diode-like (VD > 0) modes of the p-OFET. We find a higher current drive in the reverse diode-like mode compared to normal FET-like mode. The reverse mode has clearly defined OFF and ON states versus the drain voltage and non-saturated output characteristics, which makes it suitable for the use in RF and analog applications of OFETs.


Published in:
Microelectronic Engineering, 88, 8, 2496–2499
Year:
2011
Publisher:
Elsevier
ISSN:
0167-9317
Keywords:
Laboratories:




 Record created 2011-01-25, last modified 2018-03-17

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