On performance of series connected CMOS vertical hall devices

Series connected (stacked) CMOS vertical Hall devices were analyzed on the basis of performance of a single five contacts device biased at different common mode voltages with respect to the substrate. The uneven influence of junction field effect on residual offset voltage, sensitivity and residual offset equivalent magnetic field was studied. It was shown that though junction field effect leads to some increase in offset voltage for devices with higher common mode, this effect can be minimized through suitable biasing.


Published in:
2008 26Th International Conference On Microelectronics, Vols 1 And 2, Proceedings, 337-340
Presented at:
26th International Conference on Microelectronics (MIEL 2008), Nis, SERBIA, May 11-14, 2008
Year:
2008
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
Keywords:
Laboratories:




 Record created 2010-11-30, last modified 2018-09-13


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