A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV/root Hz. The receiver consists of the reception coil, an on-chip tuning capacitor an LNA and a 50 Omega output buffer. The system is designedfor operation in a B-0-field of 1.5 T corresponding to a frequency of 63MHz. It is implemented in a 0.35 mu m CMOS high voltage process and occupies a chip area of 500 mu m x 760 mu m.


Published in:
13Th International Conference On Biomedical Engineering, Vols 1-3, 23, 89-93
Presented at:
13th International Conference on Biomedical Engineering (ICBME), Singapore, SINGAPORE, Dec 03-06, 2008
Year:
2009
Publisher:
Springer, 233 Spring Street, New York, Ny 10013, United States
ISBN:
978-3-540-92840-9
Keywords:
Laboratories:




 Record created 2010-11-30, last modified 2018-03-18


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