Way Stealing: Cache-assisted Automatic Instruction Set Extensions

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the register file alone and does not require expensive coherence protocols, as it does not add memory elements to the processor. When enhanced with Way Stealing, ISE identification flows detect more opportunities for acceleration than prior methods; consequently, Way Stealing can accelerate applications to up to 3.7x, whilst reducing the memory sub-system energy consumption by up to 67%, despite data-cache related restrictions.

Published in:
Dac: 2009 46Th Acm/Ieee Design Automation Conference, Vols 1 And 2, 31-36
Presented at:
46th ACM/IEEE Design Automation Conference (DAC 2009), San Francisco, CA, Jul 26-31, 2009
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

 Record created 2010-11-30, last modified 2018-03-18

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