Scalable instruction set simulator for thousand-core architectures running on GPGPUs

Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.


Published in:
Proceedings of the IEEE 2010 International Conference on High Performance Computing and Simulation (HPCS 2010), 1, 1, 459-466
Presented at:
IEEE 2010 International Conference on High Performance Computing and Simulation (HPCS 2010), Caen, France, June 28-July 2, 2010
Year:
2010
Publisher:
New York, IEEE Press
ISBN:
978-1-4244-6827-0
Keywords:
Laboratories:




 Record created 2010-11-05, last modified 2018-01-28

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