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conference paper
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
2010
Proceedings of the IEEE 2010 International Conference on High Performance Computing and Simulation (HPCS 2010)
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
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Name
HPCS2010-05547092.pdf
Access type
openaccess
Size
866.36 KB
Format
Adobe PDF
Checksum (MD5)
c402161096bdc9690281352deca1726d